Currently, semiconductor devices include a plurality of circuits, which form an integrated circuit (IC) including chips (e.g., chip back end of line, or “BEOL”), thin film packages and printed circuit boards. Integrated circuits can be useful for computers and electronic equipment and can contain millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate. For the device to be functional, a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the device. Efficient routing of these signals across the device can become more difficult as the complexity Efficient routing of these signals across the device can become more difficult as the complexity and number of integrated circuits are increased. Thus, the formation of multilevel or multilayered interconnection schemes such as, for example, dual damascene wiring structures, have become more desirable due to their efficacy in providing high speed signal routing patterns between large numbers of transistors on a complex semiconductor chip. Within the interconnection structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate.
Presently, interconnect structures formed on an integrated circuit chip consists of at least about 2 to 8 wiring levels (See, for example, FIG. 1) fabricated at a minimum lithographic feature size designated about 1× (referred to as “thinwires”) and above these levels are about 2 to 4 wiring levels fabricated at a width equal to about 2× and/or about 4× the minimum width of the thinwires (referred to as “fatwires”). In one class of structures, the thinwires are formed in a low dielectric constant (k) organosilicate glass (OSG) dielectric layer, and the fatwires are made in a silicon dioxide dielectric layer having a dielectric constant of about 4. The OSG typically contains elements of Si, C, O and H, and is sometimes referred to as SiCOH dielectrics. These dielectrics have a dielectric constant that is below 4.0, typically the dielectric constant of OSG dielectrics is between 2.8-3.1.
In typical trench or via-first integration strategies, one of the challenges during the creation of the line level structure in dual damascene processing is to minimize line height variations (and hence line resistance variance) within a wafer and within a lot. These line height variations can arise owing to occasional etch rate non-uniformities within the employed plasma process dependent on pattern density and/or feature aspect ratio variations or due to variations in the interlevel dielectric (ILD) film thickness. To compensate for such effects, an etch stop layer (ESL) for line levels (Mx+1 levels, where x is a positive integer) can be desirable for maintaining within wafer and within lot uniformity such that line resistance values are within design manual specifications with minimal variability; thus enabling a more manufacturable process.
Typical ESLs employed for alleviating such effects include various permutations of SiC (SiCNxHy) or Si3N4 (SiON) are of higher dielectric constant (k≧5.0) than that of the ILD materials employed for 90 nm back-end-of-the-line (BEOL) technologies (k of approximately 2.8 to 3.1); thus, though addressing the issue of line height uniformity and line level resistance variance, prior art ESLs decrease overall device performance by increasing the effective dielectric constant, keff, of the structure.
In addition to the above problem concerning prior art ESLs, there is an ongoing trend of replacing traditional ILDs with low-k dielectrics that are porous. The use of porous ILD materials for 65 nm and subsequent BEOL technologies also introduces the concept of line height control and consequent variance in metal line resistances. Since typically BEOL processing conditions would etch a low-k dielectric hardmask faster than the underlying porous low-k material, the issue in line height control and resistance variation is perhaps made even more severe for these technologies.
In view of the above drawbacks with prior art interconnect structures, there is a need for providing new and improved interconnect structures in which the line height variation and hence the line resistance variance is minimized.